It is well-known in the art of electronic device manufacturing to test, and/or "burn-in," various electronic sub-components before assembling them into a larger device. For example, computer chips are frequently individually connected in a burn-in system for the purpose of ensuring that all of the desired electronic circuits in each chip are operational. The burn-in process accelerates aging of the chips and thus allows defective chips to be identified and discarded early in the manufacturing process. This is desirable because it allows the manufacturer to avoid the expense that would otherwise be wasted by constructing a larger, more expensive device containing the defective chip. In addition to burn-in, computer chips and other integrated circuits may be subjected to various other testing operations. The term "testing" as used herein is intended to encompass and include bum-in operations.
In a burn-in operation, each chip, integrated circuit (IC), or other electronic component, each of which is hereinafter referred to as a "device under test" or "DUT," is connected to several electronic leads. These leads typically take the form of an array of small solder buttons that are positioned to correspond to electronic leads on the under-surface of the DUT. The DUT is placed on the arrayed leads so that an electrical connection is made at each desired point.
During the burn-in or test operation, heat is generated by the passage of current via the leads through the various circuits on the DUT. Heretofore, ICs were less powerful and, correspondingly, the amount of power consumed during burn-in of a computer chip was relatively small. For this reason, the amount of heat generated was such that burn-in devices could be air-cooled in most cases. With the advent of newer, more powerful chips, the amount of heat generated during burn-in has multiplied ten-fold, from about 3-10 watts, to 30-100 watts or more.
In addition, the increasing cost of chip packaging has motivated manufacturers to advance the burn-in step so that it is carried out before, rather than after, final packaging. This allows manufacturers to save the cost of packaging a defective chip, but means that the burn-in operation must be carried out on partially packaged ICs, where the silicon die itself may be exposed. Partially packaged ICs are less robust and more susceptible to damage than fully packaged chips. Thus, the burn-in operation cannot subject the DUTs to excessive or uneven forces.
Because the burn-in must be carried out at a controlled temperature, and because the chips cannot be exposed to temperature extremes, it is imperative that the significant heat generated during burn-in be removed. Air cooling does not provide sufficient cooling without a very large heat sink. Liquid cooling, using an electrically insulating fluid has been tried, but has proven nonviable for very high power DUTs. At the same time, burning-in or testing a partially packaged chip raises new considerations over burning-in or testing a fully packaged chip. For example, partially packaged chips are not typically adapted to readily dump heat at the required rate.
It is known that high-power transistors generate comparable amounts of heat during burn-in operations. However, the configuration of transistors and conventional transistor packages is such that cooling systems that are designed for transistor burn-in devices cannot readily be adapted to cool IC devices. In addition, transistors are typically sealed within durable metal or plastic packages, so that the handling concerns that arise in the context of burning in chips do not arise in transistor burn-in devices. Furthermore, as compared to the volume of high power transistors that require testing, the volume of ICs that must be tested is so many times greater that cost factors that are not as significant in the context of transistor testing become prohibitive when contemplated in the context of chip testing.
In addition to the problems associated with providing sufficient cooling capacity to a given burn-in device and providing a heat transfer surface does not limit that capacity, problems arise from the fact that the amount of heat generated during burn-in or testing varies significantly from DUT to DUT. It has been found that in some instances, the amount of heat generated varies by as much as two orders of magnitude. This variance make it difficult to simultaneously burn-in several devices, as a cooling system that adequately cools the DUTs that generate greater amounts of heat will over-cool the DUTs that generate less heat, causing their temperatures to fall below the desired burn-in temperature range. Conversely, a cooling system that properly cools the DUTs that generate lesser amounts of heat will under-cool the DUTs that generate more heat, causing their temperatures to rise above the desired burn-in temperature range.
Hence, it is desired to provide a DUT burn-in device that is capable of simultaneously removing at least 30-100 watts of heat from each of several chips, while maintaining the temperature of each DUT within a narrow desired range. Furthermore, the preferred device should be capable of maintaining the DUTs within the prescribed temperature even though the DUTs produce amounts of heat that may vary by more than an order of magnitude and even though some DUTs may generate as little as 3 watts of heat. The preferred device should also be readily incorporated into a system capable of simultaneously processing multiple DUTs. These objectives require that the device be capable of compensating for variance in heat generation between DUTs that are being burned in simultaneously. The preferred device should be able to handle unpackaged chips without damaging them either before, during or after the burn-in process. It is further desired to provide a burn-in device that is commercially viable in terms of cost, labor and reliability.